In a semiconductor device such as LSI (Large Scale Integration) operable at a low voltage, for the purpose of reducing a power consumption by interrupting a power supply to a circuit block which is not used in the semiconductor device, a power gating technique which performs on/off control of the power with respect to the circuit block in accordance with a use state (presence/absence of use) of the circuit block is employed. In the power gating technique, a performance of power switch which switches whether or not the power supply is performed with respect to the circuit block (power domain) in the semiconductor device, is important.
For example, when a power supply with respect to a certain circuit block is started, there is a need to suppress a large current (inrush current) which flows momentarily when the power is turned on, in order not to exert an influence on another circuit block which is already operated. As a method of suppressing the inrush current, there is a method in which a plurality of stages of power switches are provided as illustrated in FIG. 11.
FIG. 11 is a diagram illustrating an example of configuration of conventional power switches. There are provided a first power switch 1101A having a low (weak) capability of driving each logic block (circuit block, power domain) 1103, and a second power switch 1101B having a high (strong) capability of driving the logic block (circuit block, power domain) 1103. When a supply of power to the logic block 1103 is started, the second power switch 1101B is driven by being delayed with respect to the first power switch 1101A, with the use of control signals PWCTLA and PWCTLB supplied via inverters 1102A and 1102B, respectively. As described above, the first power switch 1101A is first turned into an on state to moderately supply the power to the logic block 1103, and thereafter, the second power switch 1101B is turned into an on state to supply, to the logic block 1103, the power with which the logic block 1103 can be normally operated, thereby suppressing the inrush current when the power is turned on.
Here, in a semiconductor device operable at a low voltage, an on-resistance of a transistor is large. If a size of the transistor is increased to reduce the on-resistance of the transistor, a circuit area is inevitably increased. As countermeasures against this, by using, as a transistor of a power switch, for example, a DtMOS (Dynamic threshold MOS) transistor driven by connecting a gate and a body region thereof, it is possible to suppress the increase in the circuit area while reducing the on-resistance. Further, when bodies of transistors are driven while providing a delay thereto, a driving in a plurality of stages as illustrated in FIG. 11 can be performed.
In order to realize the driving of the plurality of stages of the power switches as described above, the circuit area is increased since a control circuit (control function) for the power switches is provided. For example, there can be considered a method in which the control circuit is not provided, and it is designed to obtain RC delay by forming a resistor (R) by a wiring, a diffusion layer or the like, and with the use of a capacitance (C) such as a capacitance of a capacity cell, and a source-drain capacitance of a transistor of the power switch, to thereby drive the plurality of stages of the power switches while providing the delay thereto. However, to form the resistor for obtaining the RC delay by using the wiring, the diffusion layer or the like, is not realistic in terms of mounting, since an area becomes very large.
As a resistor in a semiconductor device, there is a well resistor made of a semiconductor region formed in a semiconductor substrate, for example (refer to Patent Documents 1 to 3 and the like, for example). Regarding the well resistor, a technique in which an increase in an area is suppressed by forming a polysilicon resistor, via an insulating region, on a well resistor formed in a semiconductor substrate, a technique in which a resistance value is controlled by changing an impurity concentration of SOI (Semiconductor On Insulator) layer, have been proposed.
Patent Document 1: Japanese Laid-open Patent Publication No. 2008-71925
Patent Document 2: Japanese Laid-open Patent Publication No. 2007-294805
Patent Document 3: Japanese Laid-open Patent Publication No. 2012-160652